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application/pdfIEEEIEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control;2019;66;2;10.1109/TUFFC.2018.2883830Digital electronicsfield-programmable gate array (FPGA)frequency stabilityphase-locked loop (PLL)phase noisePhase Noise and Frequency Stability of the Red-Pitaya Internal PLLAndrea Carolina Cardenas OlayaClaudio Eligio CalossoJean-Michel FriedtSalvatore MicalizioEnrico Rubiola
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control412 Feb. 201926610.1109/TUFFC.2018.2883830416
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